Atomic-Scale Patterning of Arsenic in Silicon by Scanning Tunneling Microscopy.
Taylor J Z StockOliver WarschkowProcopios C ConstantinouJuerong LiSarah FearnEleanor CraneEmily V S HofmannAlexander KölkerDavid R McKenzieSteven R SchofieldNeil J CursonPublished in: ACS nano (2020)
Over the past two decades, prototype devices for future classical and quantum computing technologies have been fabricated by using scanning tunneling microscopy and hydrogen resist lithography to position phosphorus atoms in silicon with atomic-scale precision. Despite these successes, phosphine remains the only donor precursor molecule to have been demonstrated as compatible with the hydrogen resist lithography technique. The potential benefits of atomic-scale placement of alternative dopant species have, until now, remained unexplored. In this work, we demonstrate the successful fabrication of atomic-scale structures of arsenic-in-silicon. Using a scanning tunneling microscope tip, we pattern a monolayer hydrogen mask to selectively place arsenic atoms on the Si(001) surface using arsine as the precursor molecule. We fully elucidate the surface chemistry and reaction pathways of arsine on Si(001), revealing significant differences to phosphine. We explain how these differences result in enhanced surface immobilization and in-plane confinement of arsenic compared to phosphorus, and a dose-rate independent arsenic saturation density of 0.24 ± 0.04 monolayers. We demonstrate the successful encapsulation of arsenic delta-layers using silicon molecular beam epitaxy, and find electrical characteristics that are competitive with equivalent structures fabricated with phosphorus. Arsenic delta-layers are also found to offer confinement as good as similarly prepared phosphorus layers, while still retaining >80% carrier activation and sheet resistances of <2 kΩ/square. These excellent characteristics of arsenic represent opportunities to enhance existing capabilities of atomic-scale fabrication of dopant structures in silicon, and may be important for three-dimensional devices, where vertical control of the position of device components is critical.