Low-voltage self-assembled indium tin oxide thin-film transistors gated by microporous SiO 2 treated by H 3 PO 4 .

Ultralow-voltage (0.8 V) thin-film transistors (TFTs) using self-assembled indium-tin-oxide (ITO) as the semiconducting layer and microporous SiO 2 immersed in 5% H 3 PO 4 for 30 minutes with huge electric-double-layer (EDL) capacitance as the gate dielectric are fabricated at room temperature. The huge EDL specific capacitance is 8.2 μF cm -2 at 20 Hz, and about 0.7 μF cm -2 even at 1 MHz. Both enhancement mode ( V th = 0.15 V) and depletion mode ( V th = -0.26 V) operation are realized by controlling the thickness of the self-assembled ITO semiconducting layer. Electrical characteristics with the equivalent field-effect mobility of 65.4 cm 2 V -1 s -1 , current on/off ratio of 2 × 10 6 , and subthreshold swing of 80 mV per decade are demonstrated, which are promising for fast-switching and low-power electronics on temperature-sensitive substrates.