A Gate Programmable van der Waals Metal-Ferroelectric-Semiconductor Vertical Heterojunction Memory.

Ferroelectricity, one of the keys to realize non-volatile memories owing to the remanent electric polarization, has been an emerging phenomenon in the two-dimensional (2D) limit. Yet the demonstrations of van der Waals (vdW) memories using 2D ferroelectric materials as an ingredient are very limited. Especially, gate-tunable ferroelectric vdW memristive device, which holds promises in future multi-bit data storage applications, remains challenging. Here, we show a gate-programmable multi-state memory by vertically assembling graphite, CuInP 2 S 6 , and MoS 2 layers into a metal(M)-ferroelectric(FE)-semiconductor(S) architecture. The resulted devices seamlessly integrate the functionality of both FE-memristor (with ON-OFF ratios exceeding 10 5 and long-term retention) and metal-oxide-semiconductor field effect transistor (MOS-FET). It thus yields a prototype of gate tunable giant electroresistance with multi-levelled ON-states in the FE-memristor in the vertical vdW assembly. First-principles calculations further reveal that such behaviors originate from the specific band alignment between the FE-S interface. Our findings pave the way for the engineering of ferroelectricity-mediated memories in future implementations of 2D nanoelectronics. This article is protected by copyright. All rights reserved.