Terrace-confined guided growth of high-density ultrathin silicon nanowire array for large area electronics.

Ultrathin silicon nanowires (SiNWs) are ideal 1D channels to construct high performance nanoelectronics and sensors. We here report on a high-density catalytic growth of orderly ultrathin SiNWs, with diameter down to D_nw=27±2 nm and narrow NW-to-NW spacing of only S_nw~80 nm, without the use of high-resolution lithography. This has been accomplished via a terrace-squeezing strategy, where tiny indium (In) droplets move on sidewall terraces to absorb precoated amorphous Si layer as precursor and produce self-aligned SiNW array. It is found that, under proper parameter control, a tighter terrace-step confinement can help to scale the dimensions of the SiNW array down to the extremes that have not been testified before, while maintaining still a stable guiding growth over complex contours. Prototype SiNW field effect transistors demonstrate a high Ion/Ioff current ratio ~10^7, low leakage current of ~0.3 pA and steep subthreshold swing of 220 mV/dec. These results highlight the unexplored potential of catalytic growth in advanced nanostructure fabrication that is highly relevant for scalable SiNW logic and sensor applications.