Synthesis of Vacancy-Controlled Copper Iodide Semiconductor for High-Performance p-Type Thin-Film Transistors.

Copper iodide (CuI) has emerged as a promising p-type semiconductor material owing to its excellent carrier mobility, high transparency, and solution processability. Although CuI has potential for numerous applications, including perovskite solar cells, photovoltaic devices, and thin-film transistors (TFTs), the close relationship between the anion vacancy generation and the charge transport mechanism in CuI-based devices is underexplored. In this study, we propose solution-processed p-type CuI TFTs which were subject to the thermal annealing process in air and vacuum atmospheres at temperatures of 100, 200, and 300 °C. The chemical states and surface morphologies of the CuI thin films were systematically investigated, revealing the generation of iodine vacancy states and the reduction of carrier concentration, as well as increased film density and grain size according to the annealing condition. Further, the effective role of the Al 2 O 3 passivation layer on the electrical characteristics of the solution-processed CuI TFTs is demonstrated for the first time, where the Al 2 O 3 precursor greatly enhanced the electrical performance of the CuI TFTs, exhibiting a field-effect mobility of 4.02 cm 2 /V·s, a subthreshold swing of 0.61 V/decade, and an on/off current ratio of 1.12 × 10 4 , which exceed the values of CuI TFTs reported so far. Based on the synergistic effects of the annealing process and the passivation layer that engineered the iodine vacancy state and morphology of CuI, the proposed CuI TFTs with the Al 2 O 3 passivation layer showed excellent reliability under 100 times repeated operation and long-term stability over 216 h, where the transfer curves slightly shifted in the positive direction of 1.36 and 1.88 V measured at a current level of 10 -6 A for the reliability and stability tests, respectively. Thus, this work opens a new window for solution-processed p-type CuI TFTs with excellent stability for developing next-generation complementary logic circuits.