Hybrid 2D/CMOS microchips for memristive applications.

Exploiting the excellent electronic properties of two-dimensional (2D) materials to fabricate advanced electronic circuits is a major goal for the semiconductors industry 1-2 . However, most studies in this field have been limited to the fabrication and characterization of isolated large (>1µm 2 ) devices on unfunctional SiO 2 /Si substrates. Some studies integrated monolayer graphene on silicon microchips as large-area (>500µm 2 ) interconnection 3 and as channel of large transistors (~16.5µm 2 ) 4-5 , but in all cases the integration density was low, no computation was demonstrated, and manipulating monolayer 2D materials was challenging because native pinholes and cracks during transfer increase variability and reduce yield. Here we present the fabrication of high-integration-density 2D/CMOS hybrid microchips for memristive applications - CMOS stands for complementary metal oxide semiconductor. We transfer a sheet of multilayer hexagonal boron nitride (h-BN) onto the back-end-of-line (BEOL) interconnections of silicon microchips containing CMOS transistors of the 180nm node, and finalize the circuits by patterning the top electrodes and interconnections. The CMOS transistors provide outstanding control over the currents across the h-BN memristors, which allows us to achieve endurances of ~5 million cycles in memristors as small as ~0.053µm 2 . We demonstrate in-memory computation by constructing logic gates, and measure spike-timing dependent plasticity (STDP) signals that are suitable for the implementation of spiking neural networks (SNN). The high performance and the relatively-high technology readiness level achieved represent a significant advance towards the integration of 2D materials in microelectronic products and memristive applications.