A general one-step plug-and-probe approach to top-gated transistors for rapidly probing delicate electronic materials.

The miniaturization of silicon-based electronics has motivated considerable efforts in exploring new electronic materials, including two-dimensional semiconductors and halide perovskites, which are usually too delicate to maintain their intrinsic properties during the harsh device fabrication steps. Here we report a convenient plug-and-probe approach for one-step simultaneous van der Waals integration of high-k dielectrics and contacts to enable top-gated transistors with atomically clean and electronically sharp dielectric and contact interfaces. By applying the plug-and-probe top-gate transistor stacks on two-dimensional semiconductors, we demonstrate an ideal subthreshold swing of 60 mV per decade. Using this approach on delicate lead halide perovskite, we realize a high-k top-gate CsPbBr 3 transistor with a low operating voltage and a very high two-terminal field-effect mobility of 32 cm 2  V -1  s -1 . This approach can be extended to centimetre-scale MoS 2 and perovskite and generate top-gated transistor arrays, offering a rapid and convenient way of accessing intrinsic properties of delicate emerging materials.