Login / Signup

Dielectric-Engineered High-Speed, Low-Power, Highly Reliable Charge Trap Flash-Based Synaptic Device for Neuromorphic Computing beyond Inference.

Joon Pyo KimSeong Kwang KimSeohak ParkSong-Hyeon KukTaeyoon KimBong Ho KimSeong-Hun AhnYong-Hoon ChoYeonJoo JeongSung-Yool ChoiSang Hyeon Kim
Published in: Nano letters (2023)
The coming of the big-data era brought a need for power-efficient computing that cannot be realized in the Von Neumann architecture. Neuromorphic computing which is motivated by the human brain can greatly reduce power consumption through matrix multiplication, and a device that mimics a human synapse plays an important role. However, many synaptic devices suffer from limited linearity and symmetry without using incremental step pulse programming (ISPP). In this work, we demonstrated a charge-trap flash (CTF)-based synaptic transistor using trap-level engineered Al 2 O 3 /Ta 2 O 5 /Al 2 O 3 gate stack for successful neuromorphic computing. This novel gate stack provided precise control of the conductance with more than 6 bits. We chose the appropriate bias for highly linear and symmetric modulation of conductance and realized it with very short (25 ns) identical pulses at low voltage, resulting in low power consumption and high reliability. Finally, we achieved high learning accuracy in the training of 60000 MNIST images.
Keyphrases
  • big data
  • high speed
  • artificial intelligence
  • prefrontal cortex
  • endothelial cells
  • machine learning
  • blood pressure
  • atomic force microscopy
  • high resolution
  • virtual reality