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Ultimate low leakage and EOT of high- κ dielectric using transferred metal electrode.

Weiqi DangZheyi LuBei ZhaoBo LiJia LiHongmei ZhangRong SongMongur HossainZhikai LeYuan LiuXidong Duan
Published in: Nanotechnology (2022)
The increase of gate leakage current when the gate dielectric layer is thinned is a key issue for device scalability. For scaling down the integrated circuits, a thin gate dielectric layer with a low leakage current is essential. Currently, changing the dielectric layer material or enhancing the surface contact between the gate dielectric and the channel material is the most common way to reduce gate leakage current in devices. Herein, we report a technique of enhancing the surface contact between the gate dielectric and the metal electrode, that is constructing an Au/Al 2 O 3 /Si metal-oxide-semiconductor device by replacing the typical evaporated electrode/dielectric layer contact with a transferred electrode/high- κ dielectric layer contact. The contact with a mild, non-invasive interface can ensure the intrinsic insulation of the dielectric layer. By applying 2-40 nm Al 2 O 3 as the dielectric layer, the current density-electrical field ( J - E ) measurement reveals that the dielectric leakage generated by the transferred electrode is less than that obtained by the typical evaporated electrode with a ratio of 0.3 × 10 1  ∼ 5 × 10 6 at V bias  = 1 V. Furthermore, at J  = 1 mA cm -2 , the withstand voltage can be raised by 10 0 -10 2 times over that of an evaporated electrode. The capacitance-voltage ( C - V ) test shows that the transferred metal electrode can efficiently scale the equivalent oxide layer thickness (EOT) to 1.58 nm, which is a relatively smaller value than the overall reported Si-based device's EOT. This finding successfully illustrates that the transferred electrode/dielectric layer's mild contact can balance the scaling of the gate dielectric layer with a minimal leakage current and constantly reduce the EOT. Our enhanced electrode/dielectric contact approach provides a straightforward and effective pathway for further scaling of devices in integrated circuits and significantly decreases the overall integrated circuit's static power consumption (ICs).
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